Description
The RISC-V microconference focuses on the development of RISC-V.
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21/09/2021, 07:00
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ATISH PATRA (Western Digital), Mr Kumar Sankaran (ventana micro), Rahul Pathak, Mayuresh Chitale21/09/2021, 07:05
The RISC-V platform specification[1] describes a minimum set of hardware/software requirements to ensure the interoperability of software across compatible platforms. Currently, it defines two platforms i.e. OS-A platforms capable of booting rich operating systems such as Linux, FreeBSD, Windows and M platform aimed to work with RTOS and baremetal. The platform specification is currently under...
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Anup Patel (Western Digital)21/09/2021, 07:45
The RISC-V Advanced Interrupt Architecture (RISC-V AIA) and RISC-V Advanced CLINT (RISC-V ACLINT) are non-ISA specifications which define next generation interrupt controller, timer, and inter-processor interrupt (IPI) devices for RISC-V platforms. The RISC-V AIA and ACLINT devices will support wired interrupts, message signaled interrupts (MSIs), virtualized message signaled...
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Sunil V L21/09/2021, 08:30
RISC-V platform specification mandates the Advanced Configuration and Power Interface(ACPI) as the Hardware discovery mechanism for the server class platforms. There are some new ACPI tables that need to be defined for RISC-V. Code changes are required in qemu, tianocore(EDK2), and OS. This is still a work in progress but the talk will provide details about the planned specification updates...
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Mr Ren Guo, Mr Wei Fu, Mr Shaohua Liu21/09/2021, 09:00
D1 is Allwinner's first SoC based on the RISC-V ISA. It integrates the 64-bit C906 core of Ali T-Head, supports RVV, 1GHz frequency. Because some of the features are not included in the RISC-V spec, Linux upstream met some problems. Let's review and discuss the issues:
- Birdview of D1 & current status of the drivers (By Shaohua)
- About custom PBMT (Page Based Memory Type) in D1 for...
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Kito Cheng (SiFive), Palmer Dabbelt (Google)21/09/2021, 10:00
ifunc is a widely used mechnish for specialized those performance
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critical functions in glibc, like memcpy, strcmp and strlen.
It’s not used in upstream glibc for RISC-V yet, but with several new
extensions becoming ratified soon, users will desire to have
vector-optimized routines to boost their program.
It’s a generic infrastructure for GNU toolchain, so we don’t need too
much work to ... -
Philipp Tomsich (VRULL GmbH), Christoph Müllner (SBA Research)21/09/2021, 10:30
Architectures competing with RISC-V have expended considerable time and resources on optimizing their development tools for improved performance on industry-standard benchmarks. For the future growth of the RISC-V ecosystem, a concerted effort to optimize the generated code for performance will be required. This effort will in a large part be independent of the underlying microarchitecture and...
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The RISC-V software eco-system is gaining momentum at breakneck speed with three new Linux development platforms available this year. The new platforms bring new issues to deal with. One of the pressing issues is the handling of non-coherent systems as two of the three new platforms have non-coherent devices. We would like to continue the RISC-V MC platform to discuss these issues with a...
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The RISC-V software eco-system is gaining momentum at breakneck speed with three new Linux development platforms available this year. The new platforms bring new issues to deal with. One of the pressing issues is the handling of non-coherent systems as two of the three new platforms have non-coherent devices. We would like to continue the RISC-V MC platform to discuss these issues with a...
Go to contribution page
