Description
The RISC-V microconference focuses on the development of RISC-V.
The RISC-V platform specification[1] describes a minimum set of hardware/software requirements to ensure the interoperability of software across compatible platforms. Currently, it defines two platforms i.e. OS-A platforms capable of booting rich operating systems such as Linux, FreeBSD, Windows and M platform aimed to work with RTOS and baremetal. The platform specification is currently under...
The RISC-V Advanced Interrupt Architecture (RISC-V AIA) and RISC-V Advanced CLINT (RISC-V ACLINT) are non-ISA specifications which define next generation interrupt controller, timer, and inter-processor interrupt (IPI) devices for RISC-V platforms. The RISC-V AIA and ACLINT devices will support wired interrupts, message signaled interrupts (MSIs), virtualized message signaled...
D1 is Allwinner's first SoC based on the RISC-V ISA. It integrates the 64-bit C906 core of Ali T-Head, supports RVV, 1GHz frequency. Because some of the features are not included in the RISC-V spec, Linux upstream met some problems. Let's review and discuss the issues:
- Birdview of D1 & current status of the drivers (By Shaohua)
- About custom PBMT (Page Based Memory Type) in D1 for...
ifunc is a widely used mechnish for specialized those performance
critical functions in glibc, like memcpy, strcmp and strlen.
It’s not used in upstream glibc for RISC-V yet, but with several new
extensions becoming ratified soon, users will desire to have
vector-optimized routines to boost their program.
It’s a generic infrastructure for GNU toolchain, so we don’t need too
much work to ...
Architectures competing with RISC-V have expended considerable time and resources on optimizing their development tools for improved performance on industry-standard benchmarks. For the future growth of the RISC-V ecosystem, a concerted effort to optimize the generated code for performance will be required. This effort will in a large part be independent of the underlying microarchitecture and...
