There has been growing need for increasing memory capacity in enterprise design and CXL has emerged as one of the preferred solution to meet this increasing demand. CXL and other relevant specifications have defined various mechanisms, which allow kernel to utilize the extended memory capacity.
In this presentation, an implementation of firmware support for a AArch64 compliant platform will...
CXL 3.0 introduces Dynamic Capacity Devices (DCDs) to enable highly dynamic memory pooling use cases. DCDs provide fine grained, address extent based, memory hot plug, with much lighter weight handling than for conventional device level hot plug.
This comes at the expense of complexity in software handling as the host physical address ranges are sparse, and may be added and removed...
Confidential Computing aims to provide isolation to the end user from the infrastructure provider (like a Cloud provider). The infrastructure provider should never be able to access or even handle in plain text the customer data.
CPU vendors have been extending providing solutions to achieve confidential computing on the CPU. Confidential computing needs to extend to accelerators, to that...
The emerging CXL interface provides access to storage devices via IO(block) interfaces and character(memory) interfaces. The duality of the interface requires rethinking the current upstream memory and storage subsystem to support these new devices efficiently. Historically, storage devices are considered block devices accessed through a block interface. In this case, the data should be read...
CXL is an exciting new technology for many reasons. Between promised latency improvements to new device models with CXL.mem and CXL.cache, it has the potential to push peripheral devices into very new territory. However, what is in the specs versus what reality is have been two very different things.
We'd like to generate discussion around hotplug support. The first generation of CXL...
With the introduction of CXL Type 3 Memory Devices a system may
contain multiple different memory controllers to support and provide
volatile memory. To add support of all those, generic and
architectural specific implementations across different subsystems
(CXL, PCI, ACPI, MCA, EDAC, etc.) are involved. CXL introduces
following errors:
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CXL link and protocol errors and
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CXL...
This session will provide a brief status report on emulation of CXL in QEMU: What's upstream, what's queued and what's already in development.
The bulk of the time will focus on discussion of priorities for the next year.
The limited availability of CXL 2.0 hardware, against high priority of support when such hardware is available, meant that the Linux Kernel stack has been developed and...
