Compute Express Link is a cache coherent fabric that in recent years has been gaining momentum in the industry. CXL 3.0 launched just before Plumbers 2022 (where very early discussions were had), bringing new challenges such as dynamic capacity devices and large scale fabrics, two features that bring significant challenges to Linux. There has also been controversy and confusion in the Linux kernel community about the state and future of CXL, regarding its usage and integration into, for example, the core memory management subsystem. Many concerns have been put to rest through proper clarification and setting of expectations.
CXL continues to be a fast evolving standard, with upstream kernel and tooling support often running ahead of mass availability of hardware.
From the early days of CXL, QEMU has been used for CXL system emulation. The emulated feature set continues to expand to support more advanced features, with a steadily growing group of contributors, many of whom contributed to the discussions last...
"Type-2" device support is made up of a series of new CXL features. Each of
these features warrants some discussion on it's own.
Features such as P2P, Back-Invalidate, Cache-ID configuration are all
modifications to the core required by accelerator devices.
Dan Williams has already opened up the internal memory configuration to outside
device drivers with his type-2 patch series. ...
CXL 3.0 Dynamic capacity is an exciting feature that enables flexible memory pooling across multiple hosts, facilitating dynamic addition and removal of memory allocated to each host from the common pool of memory.
The previous session (Plumbers CXL Uconf 2022) covered the introduction and general use cases of the DCD and served to bring together those interested in the feature.
Title: Adding RAS Support for CXL Port Devices
Authors: Robert Richter, Terry Bowman
CXL RAS error registers are present in all CXL HW entities. The CXL driver currently only implements RAS OS support for endpoints. Support for the following CXL entities must be added as well: CXL RCH down ports, root ports, USP/DSP switch ports, and CXL host bridges (referred hereafter as...
CXL 3 introduces sharable fabric-attached memory (FAM). I would like to lay
out some use cases and lead a discussion as to what functionality will be
needed in the cxl and dax stack to make such use cases possible.
This would start with a brief overview of DCD and tagged capacity. Tagged
capacity creates a namespace of memory allocations or regions (by tag)
that apps can use to find the...
Compute Express Link (CXL), an open-standard
interconnect protocol, overcomes architectural limitations by efficiently expanding memory capacity and bandwidth. Linux enables interleave between various memory tiers. Current presentation provides workload analysis with various memory tiers to improve system performance. Presentation provides various Hardware and Linux kernel configurations to...
CXL-aware job schedulers, memory managers, and userspace tiering solutions depend on page migration syscalls to reallocate resources across nodes. Currently, these calls enable movement of memory associated with a specific PID. Moves can be requested in coarse, process-sized strokes (as with
migrate_pages), and on specific virtual pages (via
move_pages). However, a number of profiling...