Sep 12 – 14, 2022
Europe/Dublin timezone

Restartable Sequences: Scheduler-Aware Scaling of Memory Use on Many-Core Systems

Sep 12, 2022, 5:45 PM
45m
"Lansdowne" (Clayton Hotel on Burlington Road)

"Lansdowne"

Clayton Hotel on Burlington Road

LPC Refereed Track LPC Refereed Track

Speaker

Mathieu Desnoyers (EfficiOS Inc.)

Description

Using per-core data structures in user-space for memory allocators, ring buffers, statistics counters, and other general or specialized purposes typically comes with a trade-off between speed and scaling of memory use for workloads which consist of fewer threads than available cores.

This is especially true for single-threaded processes (quite common) and for containers which are constrained to a limited number of cores on large many-core systems.

This presentation introduces per-memory-space current virtual CPU IDs extension to Restartable Sequences, which uses the scheduler knowledge about the number of concurrently running threads within a process to allocate virtual CPU ID numbers, and expose them to user-space through Restartable Sequences.

Reference: "Extending restartable sequences with virtual CPU IDs", https://lwn.net/Articles/885818/

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Primary author

Mathieu Desnoyers (EfficiOS Inc.)

Presentation materials