Sep 12 – 14, 2022
Europe/Dublin timezone

Integrated PCIe monitoring and tracing facilities

Sep 12, 2022, 1:00 PM
"Meeting 1&2" (Clayton Hotel on Burlington Road)

"Meeting 1&2"

Clayton Hotel on Burlington Road



Yicong Yang (HiSilicon)


hisi_ptt reference

hisi_pcie_pmu doc

PMU for monitoring PCIe link events

  • purpose and introduction
  • Usage and event supported

PTT for tracing and tuning PCIe link

  • purpose and introduction
  • Usage of tracing and capabilities
  • Usage of tuning and event supported

Potential Scenarios

  • performance improvement with PMU + tune
  • tracing for validating and monitoring, more convenient compared to PCIe analyzer
  • etc.

More on monitoring and tracing?

  • need feedbacks for the design, usage and future plan. What we want and what'll be more helpful?
  • possible for more platforms and devices, like PMU/PTT for a switch?
  • besides tracing TLP, possible for DLLP etc?
  • more trace/monitor facilities and events for PCIe stuff?
  • possible for standardization, either specification or software framework
  • etc.
I agree to abide by the anti-harassment policy Yes

Primary author

Yicong Yang (HiSilicon)

Presentation materials

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