Speakers
Mr
Ren GuoMr
Wei FuMr
Shaohua Liu
Description
D1 is Allwinner's first SoC based on the RISC-V ISA. It integrates the 64-bit C906 core of Ali T-Head, supports RVV, 1GHz frequency. Because some of the features are not included in the RISC-V spec, Linux upstream met some problems. Let's review and discuss the issues:
- Birdview of D1 & current status of the drivers (By Shaohua)
- About custom PBMT (Page Based Memory Type) in D1 for non-coherency
SOC - About DMA sync operations in D1
- About I-cache synchronization's acceleration in D1
- About vector 0.7.1 supported in D1
- About TLB synchronization's acceleration for T-HEAD c9xx-SMP
- Discuss the ALTERNATIVE framework
- Q & A (by Liu Shaohua, Guo Ren, Fu Wei)
2 & 3 are minimum requirements for D1 bring up, let's focus on them first. 4 - 6 could help D1 work better and we just have a quick review of them. 7 is about alternative discussion, eg: how we use the errata_list.h for dma_sync ops.
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Primary authors
Mr
Ren Guo
Mr
Wei Fu
Mr
Shaohua Liu