RISC-V Microconference Accepted into 2020 Linux Plumbers Conference

We are pleased to announce that the RISC-V Microconference has been accepted into the 2020 Linux Plumbers Conference!

The RISC-V ecosystem is gaining momentum at such an astounding speed that it wouldn’t be unfair to compare it to the early days of the Linux ecosystem’s growth. There are a plethora of Linux kernel features that have been added to RISC-V and many more are waiting to be reviewed in the mailing list. Some of them resulted from direct discussions during last year’s RISC-V microconference. For example, RISC-V has a standard boot process along with a well-defined supervisor binary specification (SBI) and cpu hotplug feature. KVM support is very close to being merged and just waiting for official ratification of the H extension. NoMMU support for Linux kernel has already been merged.

Here are a few of the expected topics and current problems in RISC-V Linux land that we would like to cover.

  • RISC-V Platform Specification Progress: Unix platform specification added the improved SBI v0.2 specification this year. We will discuss the next set of specifications that should be added to standardize the requirements for RISC-V Linux.
  • Making RISC-V Embedded Base Boot Requirement (EBBR) compatible: There are ongoing efforts to add UEFI support for RISC-V Linux kernel. As a result, RISC-V can be fully EBBR compatible. We will discuss the current progress and what’s the best approach to make that happen.
  • RISC-V 32-bit glibc port: This will include details about the 64-bit time_t problem and how RISC-V 32 is going to be the first 32-bit architecture with a 64-bit time_t. What still needs to be done for 32-bit support? How do we get this merged? We will also like to discuss the plan to test and maintain it once it is merged.
  • Developing and improving BPF JITs using formal verification.: This discussion will review our ongoing efforts of applying the Serval automated formal verification framework to BPF JITs in the Linux kernel. Serval has been used to find new bugs, verify new optimizations, and to develop a new BPF JIT for 32-bit RISC-V. We will discuss possible future roles of formal verification in the JIT development process, and how formal verification can enable future optimizations that would otherwise be difficult to test.
  • RISC-V hypervisor extension : The hypervisor extension v0.5 is already available in the latest Qemu and v0.6.1 patches are already in the mailing list. The kvm patchset has been on the mailing list and waiting to be merged. We will discuss the ongoing designs for nested hypervisor implementation.
  • An introduction of vector ISA support in RISCV Linux: We will discuss the implementation of vector support in Linux kernel, how user space can get its layout or size and the future work for Linux kernel and glibc.
  • RISC-V Linux Tracing Status: The single-step trap exception is an ancient technology that has been supported by many CPU architectures, but RISC-V ISA does not support this feature. By examining the pain points in RISC-V linux kprobe/uprobe development, we want to explore introducing a new single-step hardware mechanism to help the Linux tracing infrastructure.

Come join us and participate in the discussion on how we can improve the support for RISC-V in the Linux kernel.

We hope to see you there!

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