Speakers
Description
Benefits of Accurate Exit Latency can have:
More Accurate hrtimer Expiration
Better CPU Idle level Selection
Improved Support for Latency-Sensitive Systems
Cpu different low power state can have different exit latency. And the exit latency may be affected by:
- current cpu frequency
- Different firmware version
- Different hardware difference and etc.
So compile time static idle exit latency is not sufficient. Hence propose to have dynamic Runtime Prediction of CPU Idle-State Exit Latency
More Accurate hrtimer Expiration
Due to exit latency, the actual execution time of a timer interrupt is often later than the programmed expiration time. With an accurate estimate of exit latency, the timer expiration can be advanced accordingly, improving timer firing precision.
QQ Music
Version Max Delay (ns) Average Delay (ns)
Original 2,446,254 618,558
Original 2,859,657 664,312
Original 1,916,403 466,087
Optimized 629,050 86,448
Optimized 674,887 107,095
Optimized 868,674 102,682
Honor of Kings (30 Hz)
Version Max Delay (ns) Average Delay (ns)
Original 2,309,583 14,470
Optimized 360,256 8,234
Note that data is collected from an old kernel version and legacy qcom platform.
Better CPU Idle-State Selection
The current TOE cpuidle governor estimates idle duration using Exit Latency / 2. A more accurate exit latency estimation allows the governor to derive an idle duration closer to the actual value, leading to more appropriate idle-state selection.
Improved Support for Latency-Sensitive Systems
Accurate exit latency prediction is particularly beneficial for latency-sensitive workloads, such as:
• PREEMPT_RT systems
• Real-time applications
• Interactive workloads like audio scenario
Obtaining Accurate Exit Latency at Runtime (Monitor)
• Exit latency is fundamentally defined as:
Exit Latency = System Resume Timestamp − Wakeup Event Timestamp
• The current cpuidle governor already compares predicted idle duration against actual idle duration. However, the existing measurement only covers the interval between the last instruction before entering idle and the first instruction after wakeup. Exit latency itself is typically estimated using a static value defined in the device tree.
• In practice, exit latency varies dynamically depending on runtime conditions and system state.
• There are many possible wakeup sources. To accurately determine the wakeup-event timestamp, measurements are restricted to timer-based wakeups because the timer expiration time is known.
• To ensure measurement accuracy, only idle exits triggered exclusively by timer interrupts should be considered, i.e., the timer interrupt is the only pending interrupt when the CPU wakes up.
• CPU idle states are also dynamic. As additional CPUs enter idle, the cluster-level idle state may change. Therefore, the actual idle state must be determined dynamically both when entering and exiting idle, ensuring that collected historical data is correctly associated with the corresponding idle level.
Exit Latency Prediction (Predict)
• Exit latency is influenced by multiple factors and continuously changes during runtime.
• A sliding-window-based approach can be used to collect multiple exit-latency samples.
• Outliers are filtered out, and the average of the remaining samples is used as the predicted exit latency.
Utilizing Exit Latency (Control)
More Accurate Idle-Time Estimation
The cpuidle governor can use the predicted exit latency to improve idle-duration estimation accuracy, resulting in better idle-state selection.
Improved Timer Accuracy on Broadcast-Timer Platforms
On platforms supporting a broadcast timer, multiple CPUs may need to wake up simultaneously. Since a broadcast timer interrupt can only be delivered to a single CPU initially, additional wakeup delay is introduced for the remaining CPUs.
To compensate for this effect, the exit latencies of multiple CPUs can be accumulated and applied to the first awakened CPU, producing a more accurate timer expiration schedule.
Summary of Benefits
Accurate exit latency prediction provides the following advantages:
• More accurate idle-time estimation for the cpuidle governor.
• Improved CPU idle-state selection.
• Higher timer firing accuracy through compensation for exit latency.
• Reduced wakeup latency on broadcast-timer platforms.
• Better performance for latency-sensitive systems such as PREEMPT_RT.
Open Discussions
• During evaluation, a certain percentage of outlier samples is still observed within the sampling window. Currently, these samples are removed directly to reduce their impact on prediction accuracy.
• On platforms running multiple virtual machines, the timer virtualization mechanism may affect the effectiveness and accuracy of exit-latency prediction and compensation. Further investigation is required.