Speaker
Description
The scheduler's task wake-up logic and capacity-aware load balancing rely on arch_scale_cpu_capacity() to determine how much work a CPU can absorb. It also has logic to account for the effects of transient thermal- and power-driven capacity loss. This mechanism, known as hardware pressure, is currently not used on x86: arch_scale_cpu_capacity() returns a fixed constant on non-hybrid systems, and even on hybrid systems it is a self-normalizing ratio that hides uniform, proportional capacity loss across all cores, since the reference CPU used for normalization throttles along with the rest. No plumbing exists to feed x86 thermal/power status signals (PROCHOT, RAPL power-limitation bits, HWP capability changes) into capacity accounting.
This gap has consequences. Task placement at wake-up and EAS's
overutilized-detection gate can silently keep placing or retaining tasks on a throttled CPU, because the capacity term used for comparison never reflects the throttling; the load balancer may likewise
move tasks onto throttled CPUs. This is not a purely theoretical
concern: single-core thermal throttling is common even on non-hybrid parts, and Intel Speed Select Technology’s Core Power makes persistent, policy-driven asymmetric power allocation across cores.
This talk proposes a design for exposing hardware pressure on x86 and demonstrates it against concrete use cases on real hardware. The goal is not to present a finished solution, but to solicit feedback on whether this problem is worth solving, and if so, whether the proposed solution makes sense.