Speaker
Description
SEV-TIO is quite known by now, the upstream development is split in stages and continues. The current stages are set to support basic functionality.
The talk will focus on extended features and how AMD hardware/firmware is going to implement these. This includes:
- huge pages handling in IOMMU and KVM, how RMP works and what TMPM does in PSMASH_IO.
- IOMMU TLB flushing challenges: a hack for Turin CPU family and a proper fix in the Venice family (new behavior or invlpgb) and what Venice will do in addition to that.
- Cbit and vTOM and how we can allow simultaneous private and shared access for the same device within the same VM + a (useless) way to implement “iommu=pt”-like behavior in the guest.
- sev-guest SNP platform device and using the DMA layer for sharing memory with the hypervisor.