Speaker
Description
As Protected KVM (pKVM) progresses on arm64, achieving full isolation requires hypervisor-controlled IOMMUs to prevent DMA attacks. While there has been progress on SMMUv3 support for pKVM via trap-and-emulate on the mailing list [1], a major architectural design question remains unresolved: managing the stage-2 translation tables.
Currently, the series relies on maintaining a shadow stage-2 page tables for the SMMUv3.
Architecturally, it is possible to share these page tables between the CPU and the SMMUv3 in a similar way the kernel does SVA for stage-1, which would reduce memory overhead. However, KVM has different design constraints than user-space processes, and we are expected to run on a wide range of hardware without introducing impractical limitations or assumptions brought by SVA.
Some of the main points:
- Dealing with page faults (Pinning, BBM…)
- IO TLB invalidation and DVM
- Cache coherency of the IOMMU and page tables
The goal of this session is to discuss the viability of shared stage-2 page tables and reach a path forward for DMA isolation on pKVM.
[1] https://lore.kernel.org/all/20260501111928.259252-1-smostafa@google.com/