5–7 Oct 2026
Europe/Prague timezone

Error INJection support for RAS on RISC-V architecture

Not scheduled
20m
RISC-V MC RISC-V MC

Speaker

Mr Himanshu Chauhan (Qualcomm Technologies)

Description

Error INJection (EINJ), defined by ACPI, offers a platform-independent mechanism to inject hardware errors and validate system resilience paths. By avoiding platform-specific tooling, EINJ enables consistent testing of the Linux error-handling stack across architectures, including APEI and broader RAS workflows.

This session discuss the design and implementation strategy for enabling EINJ on RISC-V platforms. It will cover architecture-specific considerations, firmware and kernel integration points, and practical validation flows for injected error scenarios. The goal is to establish a robust, upstream-friendly approach that brings RISC-V closer to feature parity with existing ACPI-based RAS ecosystems and improves confidence in production reliability.

Author

Mr Himanshu Chauhan (Qualcomm Technologies)

Presentation materials

There are no materials yet.