Speaker
Description
Svnapot gives RISC-V an architectural way to encode contiguous PTE ranges as folded mappings, and 64K mTHP is a particularly good match
for that capability.
This session presents a patch series that enables that model through dynamic fold/unfold and a split between public and raw page-table
APIs. Public helpers preserve the logical sub-PTE view expected by core MM, while raw helpers remain available to architecture-private
users that need direct access to the encoded hardware entry. In our measurements, combining 64K mTHP with Svnapot aggregation reduces
lat_mem_rd latency by about 12% compared with non-aggregated 4K mappings, improves overall SPEC CPU performance by around 2%, and
delivers about 7% on the instruction-TLB-sensitive 520.omnetpp_r sub-benchmark.
The session will also discuss whether fold/unfold transitions can avoid intermediate TLB flushes, and examine the trade-offs between
hardware 64K pages and Svnapot-based aggregation, including the advantages and drawbacks of each and whether Svnapot should support
additional aggregation granularities beyond today’s 64K mTHP use case.