Speakers
Description
The PCI interconnect specification, the devices that implement it, and the system IOMMUs that provide memory and access control to them have become the de-facto standard for connecting high-speed components. The specification continues to expand with features spanning address translation (ATS/PRI), I/O virtualisation (SR-IOV/PASID/SVA), high-performance data movement (RDMA, P2PDMA, CXL/DOE), and hardware security (CMA, IDE, SPDM), targeting everything from server and desktop computing to embedded SoC platforms, virtualisation, and IoT devices.
The kernel code that enables these features requires tight coordination between PCI devices, the IOMMUs they sit behind, and the VFIO layer that exposes them to userspace for direct access and device passthrough. Kernel interfaces and userspace APIs across all three subsystems must evolve together to keep the overall design coherent.
Following the success of the VFIO/IOMMU/PCI MC at LPC 2017, 2019, 2020, 2021, 2022, 2023, 2024 and 2025, the 2026 edition will continue to bring together PCI, IOMMU, and VFIO developers to resolve cross-subsystem design questions that cannot be settled on individual mailing lists alone.
Video recordings from 2025 are available: LPC 2025 - VFIO/IOMMU/PCI MC. Older recordings can be found on the official Linux Plumbers Conference YouTube channel and the archived LPC 2017 VFIO/IOMMU/PCI MC web page at Linux Plumbers Conference 2017.
The tentative schedule will provide an update on the current state of the VFIO/IOMMU/PCI kernel subsystems, followed by focused discussion of current issues related to the proposed topics.
The following were outcomes of last year's successful Linux Plumbers MC:
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The TEE I/O initiative for confidential compute advanced through a phased plan spanning PCI, VFIO, IOMMUFD, and KVM. Phase 1 (PCI core support for authenticated and encrypted links via the TEE Security Manager) is largely complete, and most of the dma_buf, VFIO, and IOMMUFD infrastructure for Phase 3 (host-side private MMIO and DMA) has been merged. The critical remaining issue is KVM integration: an RFC for mapping from KVM's guest_memfd within IOMMUFD is under active review. The community also reached consensus on using Sub-Stream IDs (PASID) for hardware-level isolation when transitioning devices between shared and secure states.
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A new generic IOMMU page table infrastructure was merged in 6.19 for AMD and Intel VT-d, replacing six architecture-specific implementations with a unified codebase. Since the merge, RISC-V Svpbmt support, small VA support for AMD, and preserve/unpreserve/restore callbacks have been posted, with fixes flowing through the IOMMU tree for v7.1.
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Building on the generic page tables, design consensus was reached on the Hyper-V pvIOMMU and an RFC v1 has been posted. Key decisions: simple gIOVA without PASID is acceptable, the HV IOMMU driver will not cover ARM SMMU, per-device PASID space is required, and hypercall-based enumeration without ACPI tables is acceptable. Follow-up work is addressing IOTLB tagging with domain ID differences on Intel VT-d and AMD IOMMU.
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SDXI (Smart Data Acceleration Interface) and Smart Data Cache Injection (SDCI) via PCIe TLP Processing Hints (TPH) were presented, demonstrating up to 70% memory bandwidth reduction in 100G NIC benchmarks. Since the conference, a SDXI driver series has been posted and VFIO PCIe TPH support patches are under review.
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The PCI power control (pwrctrl) framework rework reached design consensus and has since been merged, resolving timing flaws where host controller drivers deasserted PERST# signal before endpoints were powered. The new API restores PCIe spec compliance and enables proper D3cold suspend flows, with controller drivers already adopting the new interface.
Tentative topics that are under consideration for this year include (but are not limited to):
PCI: CCIX/CXL expansion memory and accelerator management; DOE; IDE; CMA; SPDM; IOASID allocation; INTX/MSI IRQ domain consolidation; Gen-Z interconnect fabric; error handling and management (AER, DPC, APEI, EDR); power management and ASPM; P2PDMA; resource claiming/assignment consolidation; DMA ownership models; Thunderbolt, DMA, RDMA, and USB4 security.
VFIO: I/O Page Fault (IOPF) for passthrough devices; SVA interface; SR-IOV/PASID integration; PASID in SR-IOV virtual functions.
IOMMU: /dev/iommufd development; IOMMU virtualisation; IOMMU driver SVA interface; DMA-API layer interactions and the move towards generic dma-ops for IOMMU drivers; IOMMU core changes (e.g., tighter integration with the device-driver core).
If you are interested in participating in this MC and have topics to propose, please use the Call for Proposals (CfP) process. Additional topics may be added based on CfP submissions.
Otherwise, join us in discussing how to help Linux keep up with the new features added to the PCI interconnect specification. We hope to see you there!
Key Attendees:
Alex Williamson, Benjamin Herrenschmidt, Bjorn Helgaas, Dan Williams, Ilpo Järvinen, Jacob Pan, James Gowans, Jason Gunthorpe, Jonathan Cameron, Jörg Rödel, Kevin Tian, Krzysztof Wilczyński, Lorenzo Pieralisi, Lu Baolu, Manivannan Sadhasivam.
Contacts:
- Alex Williamson (alwilliamson@nvidia.com)
- Bjorn Helgaas (helgaas@kernel.org)
- Jörg Rödel (joro@8bytes.org)
- Lorenzo Pieralisi (lpieralisi@kernel.org)
- Krzysztof Wilczyński (kwilczynski@kernel.org)