Description
x86-focused material has historically been spread out at Plumbers. This will be an x86-focused microconference. Broadly speaking, anything that might affect arch/x86 is on topic, except where there may be a more focused discussion occurring, like around Confidential Computing or KVM.
This microconference would look at how to address new x86 processor features and also look back at how older issues might be made less painful. For new processor features like APX, what is coming? Are the vendors coordinating, are they coordinating enough so that Linux engineers can talk and are they compatible? For older issues like hardware security vulnerabilities, is the current approach working? If not, how should they be dealt with differently? Can new hardware features or vendor policies help?
As always, the microconference will be a great place for coordination among distributions, toolchains and users up and down the software stack. All the way from guest userspace to VMMs.
Potential Problem Areas to Address:
- Old processor support HIGHMEM64 is gone. What else can be excised from 32-bit? Errata handling, especially when there are microcode fixes
- VFM” infrastructure and new Intel Families
- Expanded x86 GPRs, (aka. APX). How can they get used in the kernel? Any ways to use them while maintaining backward compatibility
- CPU Mitigation work is still painful and error-prone.
- TLB management growing pains: INVLPGB, RAR and the complex dance of home-grown synchronization primitives in switch_mm_irqs_off()
- Microcode issues: Runtime CPU vulnerability updates if mitigated in microcode How is the “old_microcode” mechanism working?
- cpu_feature_enabled(): Friend or Foe?
Key Attendees
- Peter Zijlstra peterz@infradead.org
- Borislav Petkov - bp@alien8.de
- Dave Hansen dave.hansen@linux.intel.com
- Thomas Gleixner tglx@linutronix.de
- Kirill A. Shutemov kirill.shutemov@linux.intel.com LAM and TDX/CoCo topics
- Andrew Cooper andrew.cooper3@citrix.com
- Tom Lendacky thomas.lendacky@amd.com
- H. Peter Anvin h.peter.anvin@intel.com