Notes for Jeremy Bennett's lightning talk

    - Running out of alphabet for extension letters
    - Plan to replace with more verbose and systematic extension names

32-bit instruction formats:
    - RISC-V 32-bit opcode groups are very prohibitive for extending with custom instructions (for 32-bit opcodes)
    - PULP *Parallel Ultra Low Power)
    - Family of processors geared for low power, parallel computation.
    - PULP adds several custom extensions, and added Bitmanip/SIMD before they were even standardized (and thus are somewhat different to the upstream specifications)
    - Chips Alliance/Open Hardware group design RISC-V cores for the industry

CORE-V CV32E40P - first Open Hardware Group core (is this correct?), derived from PULP core.
	- requires a lot of work:
	- lots of software:
		- GNU tools, LLVM tools
		- RTOS
		- etc
	- lots of hardware verifications needed

Current compiler: GNU 7.1, developed from research:
    - handles ~150 new instruction types, ~350 counting the variants.
    - tramples all over current RISC-V encoding space

Work for upstreaming:
    - Move opcodes to acceptable opcode space
    - leave out custom PULP SIMD and bitmanip, take from upstream
    - port PULP gcc to latest gcc
    - choose target triplet
    - add -march architecture option for the given CORE-V

Poll: Is this the right approach?
- Yes: 7
- No: 0