Description
The Device and Specific Purpose Memory Microconference is proposed as a space to discuss topics that cross MM, Virtualization, and Memory device-driver boundaries. Beyond CXL this includes software methods for device-coherent memory via ZONE_DEVICE, physical memory pooling / sharing, and specific purpose memory application ABIs like device-dax, hugetlbfs, and guest_memfd. Some suggested topic areas include, but not limited to:
NUMA vs Specific Purpose Memory challenges
Core-MM services vs page allocator isolation
CXL use case challenges
Hotness Tracking and Migration Offloads
ZONE_DEVICE future for Accelerator Memory
ZONE_DEVICE future for CXL Memory Expansion
PMEM, NVDIMM, and DAX "legacy" challenges
Memory hotplug vs Device Memory
Memory RAS and repair gaps and challenges
Dynamic Capacity Device ABI (sparse memfd?)
Confidential Memory challenges
DMABUF beyond DRM use cases
virtiomem and virtiofs vs DAX and CXL challenges
Peer-to-peer DMA challenges
CXL Memory Pool Management
Device Memory testing
Why not the MM uConf for these topics? One of the observations from MM track at LSF/MM/BPF is that there is consistently an overflow of Device Memory topics that are of key interest to Memory device-driver developers, but lower priority to core MM developers.
Key Attendees:
Dan Williams
John Groves
Jason Gunthorpe
David Hildenbrand
John Hubbard
Alistair Popple
Gregory Price
Jonathan Cameron
Dave Jiang
Ira Weiny
Progress made on topics discussed at 2025 Plumbers:
Patches available: To online or not online CXL memory?: https://lore.kernel.org/all/20260321150404.3288786-1-gourry@gourry.net/
Patches available: CXL HDM-DB support for Linux: https://lore.kernel.org/all/20260315202741.3264295-1-dave@stgolabs.net/
Patches available: Unifying sources of page hotness information: https://lore.kernel.org/all/20260323095104.238982-1-bharata@amd.com/
Patches available: Protected DMAbufs and its dynamic memory assignment woes: https://lore.kernel.org/all/20250911135007.1275833-1-jens.wiklander@linaro.org/
Patches available: DAMON-based Pages Migration for {C,G,X}PU [un]attached NUMA nodes: https://lore.kernel.org/all/20251208062943.68824-1-sj@kernel.org/
Partially merged: FAMFS Update: Status, DAX Challenges & Use Cases: https://lore.kernel.org/all/69e7d1949ebcc_7d12a10098@iweiny -mobl.notmuch/
"Device Memory" Background:
"Device Memory" is a catch-all term for the collection of platform
technologies that add memory to a system outside of the typical "System RAM" default pool. Compute Express Link (CXL), a coherent interconnect that allows memory and caching-agent expansion over PCIe phys, is one such technology. GPU/AI accelerators with hardware coherent memory, or software coherent memory (ZONE_DEVICE::DEVICE_PRIVATE), are another example technology.
The problem is how to keep Device / Specific Purpose memory contained to its specific consumers while also offering typical core-mm services. Solutions to that problem potentially intersect mechanisms like numactl, hugetlbfs, memfd, and guest_memfd. For example, guest_memfd is a kind of specific-purpose memory allocator.
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Gregory Price (Meta)
Compressed RAM (where hardware offloads compression) presents a particularly novel problem for the kernel: the device fundamentally lies about its true capacity - while the kernel is written to assume any
struct pageit can get will always be backed by real capacity.Unlike zswap/zram - these devices provide cacheline/byte access to compressed memory, their memory can remain page-table...
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Arun George (Samsung Semiconductor), Davidlohr Bueso (Samsung Semiconductor)
The PCIe Unordered I/O (UIO) feature (introduced in v6.1) relaxes the strict ordering rules of the PCIe fabric, providing benefits such as the avoidance of head-of-line (HOL) blocking. CXL v3.2 specification incorporates P2P UIO access into the HDM space, enabling the peer access from non-CXL capable accelerators (e.g., GPUs) over the PCIe bus.
Enabling UIO in the Linux kernel involves...
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Bharata Bhasker Rao (AMD)
Hardware platforms continue to expose useful and actionable memory access information to the OS in various ways. Sources of such information include CPU-level instruction/op sampling mechanisms (like AMD IBS and ARM SPE), PMU-based precise sampling (like Intel PEBS), and device-side facilities such as the CXL Hotness Monitoring Unit (HMU). These platform-provided hints can be used by...
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