Nov 13 – 15, 2018
America/Vancouver timezone

On-chip Interconnect API Proposal

Nov 15, 2018, 12:05 PM
Junior/Ballroom-AB (Sheraton Vancouver Wall Center)


Sheraton Vancouver Wall Center



Vincent Guittot (Linaro)


Modern SoCs have multiple CPUs and DSPs that generate a lot of data flowing through the on-chip interconnects. The topologies could be multi-tiered and complex. These buses are designed to handle use cases with high data throughput, but as the workload varies they need to be scaled to avoid wasting power. Furthermore, the priority between masters can vary depending on the running use case like video playback or CPU intensive tasks. The purpose of this new API is to allow drivers to express their QoS needs for interconnect paths between the various SoC components. The requests from drivers are aggregated and the system configures the interconnect hardware to the most optimal performance and power profile.

The session will discuss the following:
- How the consumer drivers can determine their bandwidth needs.
- How to support different QoS configurations based on whether each CPU/DSP device is active or sleeping.

Primary author

Georgi Djakov


Vincent Guittot (Linaro)

Presentation materials

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