{"id":203,"date":"2020-08-01T13:48:12","date_gmt":"2020-08-01T13:48:12","guid":{"rendered":"https:\/\/www.linuxplumbersconf.org\/blog\/2020\/?p=203"},"modified":"2023-03-08T07:03:17","modified_gmt":"2023-03-08T07:03:17","slug":"risc-v-microconference-accepted-into-2020-linux-plumbers-conference","status":"publish","type":"post","link":"https:\/\/lpc.events\/blog\/current\/index.php\/2020\/08\/01\/risc-v-microconference-accepted-into-2020-linux-plumbers-conference\/","title":{"rendered":"RISC-V Microconference Accepted into 2020 Linux Plumbers Conference"},"content":{"rendered":"<p>We are pleased to announce that the RISC-V Microconference has been accepted into the 2020 Linux Plumbers Conference!<\/p>\n<p>The RISC-V ecosystem is gaining momentum at such an astounding speed that it wouldn&#8217;t be unfair to compare it to the early days of the Linux ecosystem&#8217;s growth. There are a plethora of Linux kernel features that have been added to RISC-V and many more are waiting to be reviewed in the mailing list. Some of them resulted from direct discussions during <a href=\"https:\/\/www.linuxplumbersconf.org\/event\/4\/page\/34-accepted-microconferences#risc-v\">last year&#8217;s RISC-V microconference<\/a>. For example, RISC-V has a standard boot process along with a well-defined supervisor binary specification (SBI) and cpu hotplug feature. KVM support is very close to being merged and just waiting for official ratification of the H extension. NoMMU support for Linux kernel has already been merged.<\/p>\n<p>Here are a few of the expected topics and current problems in RISC-V Linux land that we would like to cover.<\/p>\n<ul>\n<li>RISC-V Platform Specification Progress: Unix platform specification added the improved <a href=\"https:\/\/lists.riscv.org\/g\/tech-unixplatformspec\/topic\/unix_platform_working_group\/74641453\">SBI v0.2 specification<\/a> this year. We will discuss the next set of specifications that should be added to standardize the requirements for RISC-V Linux.<\/li>\n<li>Making RISC-V Embedded Base Boot Requirement (EBBR) compatible: There are ongoing efforts to add UEFI support for <a href=\"http:\/\/lists.infradead.org\/pipermail\/linux-riscv\/2020-July\/001248.html\">RISC-V Linux kernel<\/a>. As a result, RISC-V can be fully <a href=\"https:\/\/www.linux.com\/topic\/embedded-iot\/ebbr-aims-standardize-embedded-boot-process\/\">EBBR<\/a> compatible. We will discuss the current progress and what&#8217;s the best approach to make that happen.<\/li>\n<li>RISC-V 32-bit <a href=\"https:\/\/sourceware.org\/pipermail\/libc-alpha\/2020-June\/114675.html\">glibc port<\/a>: This will include details about the 64-bit time_t problem and how RISC-V 32 is going to be the first 32-bit architecture with a 64-bit time_t. What still needs to be done for 32-bit support? How do we get this merged? We will also like to discuss the plan to test and maintain it once it is merged.<\/li>\n<li>Developing and improving BPF JITs using formal verification.: This discussion will review our ongoing efforts of applying the <a href=\"https:\/\/github.com\/uw-unsat\/serval-bpf\">Serval<\/a> automated formal <a href=\"https:\/\/unsat.cs.washington.edu\/projects\/serval\/\">verification framework<\/a> to BPF JITs in the Linux  kernel. Serval has been used to find new bugs, verify new optimizations, and to develop a new BPF JIT for 32-bit RISC-V. We will discuss possible future roles of formal verification in the JIT development process, and how formal verification can enable future optimizations that would otherwise be difficult to test.<\/li>\n<li>RISC-V hypervisor extension : The hypervisor extension v0.5 is already available in the latest Qemu and v0.6.1 patches are already in the mailing list. The <a href=\"http:\/\/lists.infradead.org\/pipermail\/linux-riscv\/2020-July\/001028.html\">kvm patchset<\/a> has been on the mailing list and waiting to be merged. We will discuss the ongoing designs for nested hypervisor implementation.<\/li>\n<li>An introduction of vector <a href=\"https:\/\/lwn.net\/Articles\/822929\/\">ISA support in RISCV Linux<\/a>: We will discuss the implementation of vector support in Linux kernel, how user space can get its layout or size and the future work for Linux kernel and glibc.<\/li>\n<li>RISC-V Linux Tracing Status: The single-step trap exception is an ancient technology that has been supported by many CPU architectures, but RISC-V ISA does not support this feature.  By examining the pain points in RISC-V linux kprobe\/uprobe development,  we want to explore introducing a new single-step hardware mechanism to help the Linux tracing infrastructure.<\/li>\n<\/ul>\n<p>Come join us and participate in the discussion on how we can improve the support for RISC-V in the Linux kernel.<\/p>\n<p>We hope to see you <a href=\"https:\/\/www.linuxplumbersconf.org\/event\/7\/page\/80-accepted-microconferences#riscv-cr\">there<\/a>!<\/p>\n","protected":false},"excerpt":{"rendered":"<p>We are pleased to announce that the RISC-V Microconference has been accepted into the 2020 Linux Plumbers Conference! The RISC-V ecosystem is gaining momentum at such an astounding speed that it wouldn&#8217;t be unfair to compare it to the early days of the Linux ecosystem&#8217;s growth. There are a plethora of Linux kernel features that [&hellip;]<\/p>\n","protected":false},"author":9,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"inline_featured_image":false,"footnotes":""},"categories":[1],"tags":[19],"class_list":["post-203","post","type-post","status-publish","format-standard","hentry","category-uncategorized","tag-19"],"_links":{"self":[{"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/posts\/203","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/users\/9"}],"replies":[{"embeddable":true,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/comments?post=203"}],"version-history":[{"count":1,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/posts\/203\/revisions"}],"predecessor-version":[{"id":429,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/posts\/203\/revisions\/429"}],"wp:attachment":[{"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/media?parent=203"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/categories?post=203"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/lpc.events\/blog\/current\/index.php\/wp-json\/wp\/v2\/tags?post=203"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}